Term Quantization: Furthering Quantization at Run Time
H. T. Kung, B. McDanel, S. Zhang Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis […]
Maestro: A Memory-on-Logic Architecture for Coordinated Parallel Use of Many Systolic Arrays
H. T. Kung, B. McDanel, S. Zhang, X. Dong, C. Chen. 30th IEEE International Conference on Application-specific Systems, Architectures and […]
Full-stack Optimization for Accelerating CNNs Using Powers-of-Two Weights with FPGA Validation
B. McDanel, S. Zhang, H. T. Kung, X. Dong. 32nd ACM International Conference on Supercomputing (ICS), 2019 paper
Systolic Building Block for Logic-on-Logic 3D-IC Implementations of Convolutional Neural Networks
H. T. Kung, B. McDanel, S. Zhang, C. T. Wang, J. Cai, C. Y. Chen, V. Chang, M. F. Chen, […]
Packing Sparse Convolutional Neural Networks for Efficient Systolic Array Implementations: Column Combining Under Joint Optimization
H. T. Kung, B. McDanel, and S. Zhang 24th ACM International Conference on Architectural Support for Programming Languages and Operating […]
Adaptive Tiling: Applying Fixed-size Systolic Arrays To Sparse Convolutional Neural Networks
H. T. Kung, B. McDanel, S. Zhang International Conference on Pattern Recognition (ICPR), 2018 paper
Mapping Systolic Arrays Onto 3D Circuit Structures: Accelerating Convolutional Neural Network Inference
H. T. Kung, B. McDanel, S. Zhang IEEE Workshop on Signal Processing Systems (SiPs), 2018. paper
