Maestro: A Memory-on-Logic Architecture for Coordinated Parallel Use of Many Systolic Arrays

Maestro: A Memory-on-Logic Architecture for Coordinated Parallel Use of Many Systolic Arrays

Posted on August 21, 2019

H. T. Kung, B. McDanel, S. Zhang,  X. Dong, C. Chen.
30th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2019
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